JCET offers a full suite of assembly services to meet our customers’ semiconductor packaging needs, including leadframe, laminate, flip chip interconnect and advanced wafer level technology.
JCET differentiates itself by providing a comprehensive platform of wafer level technology that includes Fan-in Wafer Level Packaging (FIWLP), Fan-out Wafer Level Packaging (FOWLP), Integrated Passive Devices (IPD) and Through Silicon Via (TSV) to meet the increasing market demand for next generation devices with higher levels of integration, increased functionality and compact sizes.
We collaborate with customers on die and package designs to provide the best possible products in terms of performance, quality, cycle time and cost. Our comprehensive wafer level technology platform provides customers with a wide range of choices for 2.5D and 3D package integration in advanced mobile devices such as smartphones and tablets.
? Wafer Level Packages
? Flip Chip Packages
? MEMS and Sensors
? Wirebond Packages
? Discrete 分立器件