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Today’s consumers are looking for powerful, multi-functional electronic devices with unprecedented performance and speed, yet small, thin, and low cost. This creates complex technology and manufacturing challenges for semiconductor companies as they look for new ways to achieve greater performance and functionality in a small, thin, low cost device. JCET is an industry leader in providing a comprehensive platform of wafer level technology solutions including Fan-in Wafer Level Packaging (FIWLP), Fan-out Wafer Level Packaging (FOWLP), Integrated Passive Devices (IPD), Through Silicon Via (TSV), Encapsulated Chip Package (ECP), and Radio Frequency Identification (RFID).
JCET offers a wide range of wafer level technologies including embedded Wafer Level Ball Grid Array (eWLB), encapsulated Wafer Level Chip Scale Packages (eWLCSP), Wafer Level Chip Scale Packages (WLCSP), Integrated Passive Devices (IPD), Encapsulated Chip Package (ECP), and Radio Frequency Identification (RFID).